1. Field of the Invention
The present invention relates generally to a dynamic random access memory and, more particularly, to the configuration of and the operation method of a dynamic random access memory which can easily cope with decreased rated values of an operation supply voltage.
2. Description of the Background Art
In recent years, semiconductor memories are generally employed in a variety of fields. One of the semiconductor memories is called a Dynamic Random Access Memory (hereinafter referred to as a DRAM). First of all, the configuration of and the operation of a conventionally employed DRAM will be described.
FIG. 1 illustrates one example of the schematic configuration of the entire read-out portion of the conventional DRAM. Referring to FIG. 1, the DRAM comprises a memory cell array MA having memory cells of storing information arranged in a matrix of rows and columns, an address buffer AB for generating an internal address in response to an external address which is externally applied, an X decoder ADX for receiving an internal row address from the address buffer AB to select a corresponding row of the memory cell array MA, and a Y decoder ADY for receiving an internal column address from the address buffer AB to select a corresponding column of the memory cell array MA.
The address buffer AB receives a row address for designating a row of the memory cell array MA and a column address for designating a column of the memory cell array MA in a time division multiplexing manner, generates an internal row address and an internal column address at their respective predetermined timings, and applies the addresses to the respective X decoder ADX and Y decoder ADY.
In order to read-out data of a memory cell designated by the external address, the DRAM further includes sense amplifiers for sensing and amplifying the data of the memory cells connected to the row selected by a row address decode signal from the X decoder ADX, an input/output interface (I/O) for transmitting the data of one of the memory cells in the selected row, which is connected to a corresponding column, to an output buffer OB in response to a column address decode signal from the Y decoder ADY, and the output buffer OB for transmitting the memory cell data transmitted via the input/output interface (I/O) to the outside of the DRAM.
The sense amplifiers and the input/output interface (I/O) are together shown in one block SI in FIG. 1. The output buffer OB receives read-out data transmitted from the block SI and converts the data to corresponding output data Dout to output the same.
A peripheral circuit CG for control signal generation is provided so as to generate control signals for controlling various operation timings of the DRAM. The peripheral circuit CG for control signal generation generates a precharge potential V.sub.B, a word line driving signal Rn, an equalizing signal .phi..sub.E, a precharge signal .phi..sub.P, and a sense amplifier activating signal .phi..sub.S, which will be described later.
A pad PA is provided to apply an operation supply voltage to the DRAM. The pad PA being connected to an external supply terminal receives the operation supply voltage V.sub.cc externally applied and transmits an internal operation supply voltage V.sub.cc. A semiconductor chip CH has a plurality of bonding pads on its peripheral portion to provide connections between the DRAM and external devices; however, only a pad PA for a power supply is typically illustrated in FIG. 1.
FIG. 2 illustrates the schematic configuration of the memory cell array shown in FIG. 1 and of circuits related thereto. Referring to FIG. 2, the memory cell array MA comprises word lines WL1, WL2, . . . , WLn each for selecting a row of the memory cell array MA, and bit line pairs BL0, BL0, BL1, BL1, . . . BLm, BLm each for selecting a column of the memory cell array MA. The bit lines BL0, BL0, . . . , BLm, BLm have a folded bit line scheme, and two of the bit lines form one bit line pair. That is, the bit lines BL0, BL0 form a bit line pair, and the bit lines BL1, BL1 form another bit line pair. The bit lines BLm, BLm form a bit line pair in the same manner as above.
Memory cells 1 for storing information are provided at intersections of the bit lines BL0, BL0, . . . , BLm, BLm and the alternate word lines, respectively. That is, for each bit line pair, a memory cell 1 is connected at the intersection of a word line and either one of the bit lines in a pair.
The bit line pairs BL0, BL0, . . . , BLm, BLm each have a precharge/equalizing circuit 150 provided thereon for equalizing a potential on each of the bit lines and precharging the same to a predetermined potential V.sub.B in a standby period of the DRAM.
The bit line pairs BL0, BL0, . . . , BLm, BLm each have a sense amplifier 50 provided thereon for sensing and amplifying data of selected memory cells. The sense amplifier 50 is activated in response to a first sense amplifier driving signal .phi..sub.A and a second sense amplifier driving signal .sub.B respectively transmitted via a first signal line 14 and a second signal line 17, to detect and differentially amplify a potential difference between its corresponding bit lines in a pair.
In order to transmit the data of a selected memory cell to the output buffer OB (refer to FIG. 1), the bit line pairs BL0, BL0, . . . , BLm, BLm have transfer gates T0, and T0', T1 and T1', and Tm and Tm, provided thereon, respectively, which are turned on responsive to a column address decode signal from the Y decoder ADY and connect the corresponding bit line pair to data input/output buses I/O, I/O. The transfer gates, T0 and T0' are provided corresponding to the bit lines BL0, BL0, the transfer gates T1 and T1' to the bit lines BL1, BL1, and the transfer gates Tm and Tm' to the bit line pair BLm, BLm. A pair of the transfer gates is turned on responsive to the column address decoder signal from the Y decoder ADY, so that its corresponding bit line pair is connected to the data input/output buses I/O, I/O. The sense amplifiers 50, the transfer gates T0, T0' to Tm, Tm' and the data input/output buses I/O, I/O all correspond to the block SI shown in FIG. 1.
FIG. 3 is a detail view of the circuit configuration with respect to one of the bit line pairs in the configuration shown in FIG. 2, and is particularly a circuit diagram illustrating in detail the configuration of a device for operating the sense amplifier 50.
Referring to FIG. 3, a memory cell 1 comprises a memory capacitor 6 for storing information in the form of a charge, and a select transistor 5 which is turned on responsive to a word line driving signal Rn transmitted onto a word line 3 to connect the memory capacitor 6 to a bit line 2. The select transistor 5 is formed of an n channel insulating gate field effect transistor (hereinafter referred to as an n-FET), and has its gate connected to the word line 3 and its source connected to the bit line 2. The memory capacitor 6 has one electrode connected to the drain of the select transistor 5 via a storage node 4 and the other electrode connected to a ground potential GND.
A precharge/equalizing circuit 150 includes n-FETs 9, 10 and 12. The n-FET 9 is turned on responsive to a precharge signal .phi..sub.P transmitted via a signal line 11 for precharge signal transmission, to transmit a precharge voltage V.sub.B transmitted via a signal line 8 for precharge potential transmission to the bit line 2. The n-FET 10 is turned on responsive to the precharge signal .phi..sub.P transmitted via the signal line 11 to transmit the precharge voltage V.sub.B transmitted via the signal line 8 to a bit line 7. The n-FET 12 is turned on responsive to an equalizing signal .phi..sub.P transmitted via a signal line 13 for equalizing signal transmission and electrically shorts the bit lines 2 and 7 to equalize potentials on the bit lines 2 and 7.
A sense amplifier 50 comprises p channel insulating gate field effect transistors (hereinafter referred to as p-FETs) 15 and 16, and n-FETs 18 and 19. The sense amplifier 50 is formed of the flip-flop of a CMOS configuration. The p-FETs 15 and 16 have their gates and their one electrodes cross-coupled, and the n-FETs 18 and 19 have their gates and their one electrodes cross-coupled. The connecting point of the one electrode of the p-FET 15 and that of the n-FET 18 is connected to the bit line 2. The connecting point of the one electrode of the p-FET 16 and that of the n-FET 19 is connected to the bit line 7. The other electrodes of the p-FETs 15 and 16 are connected to a signal line 14 for transmitting a first sense amplifier driving signal .phi..sub.A. The other electrodes of the n-FETs 18 and 19 are connected to a signal line 17 for transmitting a second sense amplifier driving signal .phi..sub.B.
n-FETs 26, 27 and 28 are provided between the signal lines 14 and 17 in order to precharge and equalize potentials on the signal lines 14 and 17 to a predetermined potential V.sub.B. The n-FET 26 is turned on responsive to the precharge signal .phi..sub.P transmitted via the signal line 11 to transmit the precharge signal V.sub.B of a predetermined constant potential transmitted via the signal line 8 onto the signal line 14. The n-FET 27 is turned on responsive to the precharge signal .phi..sub.P transmitted via the signal line 11 to transmit the precharge voltage V.sub.B transmitted via the signal line 8 onto the signal line 17. The n-FET 28 is turned on responsive to the precharge signal .phi..sub.P transmitted via the signal line 11 and electrically shorts the signal lines 14 and 17 to equalize the potentials on these signal lines.
In order to operate the sense amplifier 50, a p-FET 22 is provided between the signal line 14 and a first terminal 24 for power supply potential (which corresponds to the pad PA shown in FIG. 1), which is turned on responsive to a first sense amplifier activating signal .phi..sub.S to connect the signal line 14 to a first power supply line 31.
Similarly, an n-FET 25 is provided between the signal line 17 and a second terminal 29 for power supply potential, which is turned on responsive to a second sense amplifier activating signal .phi..sub.S to connect the signal line 17 to a second power supply line 30.
The sense amplifier activating signals .phi..sub.S and .phi..sub.S are applied to the gates of the p-FET 22 and n-FET 25 via signal input terminals 23a and 23b, respectively. The power supply terminals 24 and 29 are provided by the bonding pads formed on the peripheral portion of the semiconductor chip CH forming the DRAM thereon so as to receive a predetermined potential supply from the outside of the DRAM. The terminal 24 corresponds to the pad PA.
The bit line 2 has a parasitic capacitance 20, and the bit line 7 has a parasitic capacitance 21.
In order to avoid complexity in the drawing, a single word line 3 and one memory cell 1 connected to this word line 3 are only typically illustrated in the configuration
of FIG. 3. Further, the precharge voltage V.sub.B for precharging the bit lines 2 and 7 and the signal lines 14 and 17 to a predetermined potential is normally set to be at a constant potential, half the operation supply voltage V.sub.cc.
FIG. 4 is a signal waveform diagram illustrating the operation of the circuit configuration shown in FIG. 3. FIG. 4 illustrates a signal waveform of an operation in reading information of logic "1" stored in the memory cell 1 shown in FIG. 3. Next, referring to FIGS. 3 and 4, the reading operation of the memory cell data will be described.
The precharge signal .phi..sub.P and the equalizing signal .phi..sub.E are both logical high ("H" level) in a standby state from the time t0 to the time t1. Therefore, the n-FETs 9, 10 and 12 and the n-FETs 26, 27 and 28 are all ON, so that the bit lines 2 and 7 and the signal lines 14 and 17 are held at a predetermined precharge potential V.sub.B (=V.sub.cc /2).
When the standby state ends and a memory cycle starts at the time t1, the precharge signal .phi..sub.P and the equalizing signal .phi..sub.E fall to be logical low (to the "L" level). Accordingly, the n-FETs 9, 10, 12, 26, 27 and 28 are all turned off.
When the precharge signal .phi..sub.P and equalizing signal .phi..sub.E go to the "L" level at the time t2, and then the n-FETs 9, 10, 12, 26, 27 and 28 are turned off, the internal row address is applied to the X decoder ADX from the address buffer AB shown in FIG. 1 to carry out a row selection in the memory cell array MA.
At the time t3, the word line driving signal Rn is transmitted onto a selected word line 3 (assuming that the word line 3 shown in FIG. 3 is selected), and the potential on the word line 3 rises. Accordingly, the select transistor 5 of the memory cell 1 is turned on, so that the memory capacitor 6 is connected to the bit line 2. As a result, a charge stored in the storage node 4 moves onto the bit line 2, so that the potential on the bit line 2 rises only by .DELTA.V. A value of the potential rise .DELTA.V on the bit line 2 is determined by a capacitance value C6 of the memory capacitor 6, a capacitance value C20 of the parasitic capacitance 20 of the bit line 2, and a storage voltage V4 of the storage node 4, to attain normally a value from 100 to 200 mV.
At the time t4, the sense amplifier activating signal .phi..sub.S rises while the sense amplifier activating signal .phi..sub.S falls down, and the n-FET 25 and the p-FET 22 are turned on, so that the first and second signal lines 14 and 17 are connected to the respective first and second power supply lines 31 and 30. Accordingly, the potential on the first signal line 14 starts rising, while the potential on the second signal line 17 starts falling. Due to the rising and falling of the potentials on the first and second signal lines 14 and 17, a flip-flop circuit (the sense amplifier 50) formed of the p-FETs 15, 16 and the n-FETs 18 and 19 is activated and thus starts a sense operation of memory cell data to differentially amplify a small potential difference .DELTA.V between the bit lines 2 and 7. Since a selected memory cell is not connected to the bit line 7, the potential on the bit line 7 remains at V.sub.cc /2 of a precharge level until the time t4.
In this sense operation, when the n-FET 19 is turned on due to the potential rising of .DELTA.V on the bit line 2, the charge applied to the parasitic capacitance 21 is discharged onto the second signal line 17 via the n-FET 19, resulting in the lowering of the potential on the second signal line 17. Thus the potential on the bit line 7 falls to approximately 0 V at the time t5.
Meanwhile, due to the lowered potential on the bit line 7, the p-FET 15 is turned on, so that the potential on the first signal line 14 is transmitted onto the bit line 2 via the p-FET 15, and the potential on the bit line 2 rises to the V.sub.cc level. The potential on the bit line 2 is transmitted to the storage node 4 via the select transistor 5, and then the potential level of the storage node 4 becomes the level of V.sub.cc -V.sub.TN, so that the data is rewritten in the memory cell 1. The V.sub.TN is a threshold voltage of the select transistor 5.
When amplifying operations of signal potentials on the bit lines 2 and 7 are completed, and the potentials thereof are respectively established at the supply potential V.sub.cc level and the ground potential GND level, a column of the memory cell array is selected by an address decode signal from the column decoder ADY (see FIG. 1) before the time t8, and the bit lines 2 and 7 are connected to the data input/output buses I/O and I/O (see FIG. 2), so that information of the memory cell 1 is read out. The foregoing describes the operations of reading, amplifying and rewriting the data of the memory cell. With a series of these operations completed, there comes the standby state in preparation for the next memory cycle.
That is, when the word line driving signal Rn starts falling at the time t8, and falls to the "L" level of the ground potential level at the time t9, the select transistor 5 is turned off, and the memory cell 1 is electrically separated from the bit line 2 so as to be at the standby state.
When the sense amplifier activating signals .phi..sub.S and .phi..sub.S respectively start falling and rising at the time t10, and then go to the lower level of the ground potential GND level and to the higher level of the supply voltage V.sub.cc level at the time t11, the p-FET 22 and the n-FET 25 are turned off, so that the sense amplifier is inactivated.
When the equalizing signal .phi..sub.E starts rising and the n-FET 12 is turned on at the time t12, the bit lines 2 and 7 are electrically connected to each other, so that the charge moves from the bit line 2 of the higher potential level to the bit line 7 of the lower potential level, and thus the potentials on the bit lines 2 and 7 both become a 25 precharge voltage V.sub.B (=V.sub.cc /2) at about the time t13. At the same time, turning off of the p-FET 22 and the n-FET 25 causes shifting of the charge between the first and second signal lines 14 and 17 in the high impedance state, and the bit lines 2 and 7, and thus makes the potential levels on the signal lines 14 and 17 attain the values of V.sub.cc /2+.vertline.VTP.vertline. and V.sub.cc /2-V.sub.TN, respectively. Here, the V.sub.TP is a threshold voltage of the p-FETs 18 and 19.
When the precharge signal .phi..sub.P starts rising at the time t14, the n-FET 9, 10, 16, 17 and 28 start conducting, and when the precharge signal .phi..sub.P attains the "H" level of the supply voltage V.sub.cc level at the time t15, the n-FETs 9, 10, 26, 27 and 28 are all turned on. Accordingly, the precharge voltage V.sub.B is transmitted to the bit lines 2 and 7, and also the signal lines 14 and 17 are electrically connected to each other via the n-FET 28. Further, the respective potentials thereof are equalized with each other, and also a predetermined precharge voltage V.sub.B is transmitted via the n-FETs 26 and 27. Consequently, the potentials on the first and second signal lines 14 and 17 both attain the value of V.sub.cc /2.
This shifting of the precharge signal .phi..sub.P to the "H" level causes the potentials on the bit lines 2 and 7 and the signal lines 14 and 17 to be stabilized, preparing for the next reading operation.
The above described DRAM has mainly been applied to main memory devices in small- through large-scale computers. However, due to a reduction in price per bit accompanied with the increased storage capacity of the DRAM, the DRAM with reduced price per bit has also been applicable to a field of sound data processing, e.g., recordings on automatic answering telephones and electronic pocketbooks etc.
However, batteries are usually employed as a power supply in such a field. In this case, for example, employing, as the power supply, three dry batteries of 1.5 V connected in series supplies 4.5 V of a power supply voltage.
Meanwhile, since the above described standard DRAM normally employs a TTL circuit (a transistor-transistor logic circuit formed of a bipolar transistor) as its external circuit, the DRAM is designed with the supply voltage of 5 V in order to enhance its compatibility to the TTL circuit. That is, various specification values of the DRAM is selected under the operation supply voltage of 5 V, and the parameter of each of the elements constituting the DRAM is designed with the operation supply voltage of 5 V.
As described above, when the operation supply voltage of the DRAM is 4.5 V, the value of which is obtained by connecting three dry batteries in series, there is already a difference of 0.5 V between this value and a design value of 5 V; however, when the batteries are used as an operation power supply, it should be taken into consideration that a voltage drop may occur due to the battery lives, so that it should be considered in general that the voltages of the dry batteries drop from 1.5 V to 1.2 V.
When the voltage of each of the batteries is 1.2 V, the supply voltage becomes 3.6 V. That is, the DRAM need be designed so that the operation supply voltage can normally operates even at 3.6 V, in order that the DRAM can sufficiently function also in the sound data processing field employing such batteries as the operation power supply.
Two main factors are presented for the fact that the currently used DRAM does not operate at a lower supply voltage, or an operating margin is considerably reduced. The one is concerned with the necessity of fast operations. In a standard DRAM, for example, a normal access time (the required time period from supplying of an address to reading or writing of a valid data) is required to be 80-120 ns, or a cycle time (the period from the time when a signal RAS is activated to the time when data writing in/reading from one memory cell is completed to shift again to a standby state) is required to be 160-220 ns.
The operation speed of the DRAM changes depending on the operation supply voltage. The access time (the cycle time) increases as the operation supply voltage decreases, and thus the above required times cannot be satisfied. For example, in the case of the DRAM with the operation supply voltage of 5 V and the access time of 100 ns, the access time increases to 150 ns as the supply voltage decreases to 3.6 V.
The other factor is that a read-out voltage from a memory cell decreases as the supply voltage decreases, so that the memory cell data cannot be amplified normally.
In general, a problem with respect to the access time (the cycle time) occurs around 4.5 V of the supply voltage, while another problem with respect to amplification of the memory cell data occurs around 4.0 V of the supply voltage.
Therefore, it has been difficult to apply a conventional DRAM as it is to a lower supply voltage field where the batteries are employed as the power supply, such as in the sound data processing field.
A configuration is disclosed in Japanese Patent Laying-Open No. 62-232796, wherein different supply voltages are applied to the gate of a sense amplifier driving FET in order to vary the operation speed of the sense amplifier. In this prior art, to cope with a deviation of memory cell capacitance depending on process parameter, an external supply voltage is changed depending on a memory cell capacitance value, to be applied to the gate of the sense amplifier driving FET. Therefore, it is assumed that the operation supply voltage is at a fixed level, and a sense amplifier activating timing is unvaried. Consequently, when the operation power supply has a small rated value, the operating margin decreases and thus the above described problems of the conventional DRAM cannot be eliminated in the prior art.